This work is inspired by the GPS receiver stack (hardware, gateware, software) from UNSW first published in the 2006-2007 time frame known as Namuru. Technically, that looks like a wonderfully successful project! Props to Peter Mumford, Kevin Parkinson, Andrew Dempster, and everyone else on the team at UNSW! I see four main problems with carrying the results forward to a broader open source community:
This nascent project attempts to address those problems:
I started off with an SE4110L as the GPS receiver, only to find the message from Skyworks that the SE4110L is "Not recommended for new designs - replacement is SE4150L." Good thing I didn't plan to use a 19.5 MHz clock! Both chips are in-stock at Digi-Key, with identical prices.
The interface between the GPS module and the FPGA development board is chosen as Digilent's Pmod. A double-high Pmod interface carries eight user-I/O pins, which can carry the GPS clock, two ADC bits, and an I2C bus for housekeeping. I can find several off-the-shelf FPGA boards with such an interface:
The initial configuration will have an SMA connector to which a GPS active antenna (such as is available from AdaFruit) is connected.
The essential components with which to build the GPS receiver are:
|part #||Digi-Key price||function|
|SE4150L||$2.99||GPS receiver chip|
|B9415||$1.58||1575 MHz SAW filter|
|ASVTX-12||$5.81||16.368 MHz TCVXCO|
To which I add a low-noise 3.0V regulator, passives, and I2C monitoring hardware. Still, the component parts cost is only US$33 in singles, US$28.20 in 25's. Board fabrication is likely less than US$3 in moderate quantity (~50). I'm less clear on the cost of assembly. If small-volume product-ized, I can hope it would sell for under US$100.
Board design files (using gEDA) (not cleared for fab). This tentative board design is two layers, 50.8 x 20.32 mm, where the width is as required by the Pmod standard: 0.8 inch. I'm a little concerned about choosing a Pmod pin for the clock signal that routes to an FPGA GCLK pin. Then again, at 16 MHz, I probably shouldn't worry.
Before building any hardware, I'd like to see the gateware and software start to come together. Ideally, it will all fit in an LX25 so I can use the XESS board. The GPS correlators from the Namuru project are not a problem: I have a version converted to portable Verilog (no LPM instantiation) that compiles on Icarus, synthesizes on Xilinx XST, and take up 45% of the fabric of an LX25 (but I can see how to reduce that significantly). The OHWR LM32 core takes 12% of the LX25, but I'm not sure how complete this is. That should leave plenty of space to experiment with FFT-based satellite acquisition and other ideas discussed by UNSW. Open source software that might be relevant to build on:
If and when this setup works, others will be free to complain that:
But those are topics for another day.
Comments as of 2013-06-05: I haven't forgotten about this project. The board layout looks pretty much OK; the few things I might want to add are a power jumper to allow feeding 5V from a non-Pmod pin on the Pipistrello, and a test point or two. Mostly I'm trying to get to the point where I can build gateware and software to support this thing -- I really don't like building hardware that I don't have (potentially) working software for. That will also help answer questions like: do I really need external RAM, and will the design fit in an LX9?
June 5, 2013