vhd2vl

Larry Doolittle's updates of Vincenzo Liguori's VHDL to Verilog translator

Vincenzo's only release, v1.0, from 2004: Ocean Logic's download page, and source code from my mirror (18k .tar.gz)

Vincenzo has an un-released v1.1 that he kindly sent me.

My first update, v1.2, from 2005: source code (18k .tar.gz)

Mark Gonzales' update, v2.0, from 2006: also on Ocean Logic's download page, and source code from my mirror (30k .tar.gz). This version built from v1.0, not v1.2.

Preliminary (April 2008) patches to bring Mark's 2.0 code up to the level I need. Mark, if you read, this, contact me so we can coordinate another release!

Steve Haynal has an unreleased v2.1 that was forwarded to me. I'm studying it now (May 2008), and will attempt to merge it with other work. Contact me if you want to help code and/or test.

Changelog for v1.2

Grammar:

• allow NATURAL as an expression terminal symbol
• allow (name'event and exprc) as process sensitivity
• allow IS syntactic sugar in COMPONENT declaration
• add a bunch of "rem"s to the grammar
• handle inout better
• treat "signed", "unsigned", "boolean" as synonyms for "std_logic" and "std_logic_vector"

Operation:

• more complete handling of argc/argv
• if error happened, return 1 from main and remove incorrect/incomplete output files
• avoid insinuating that output Verilog is covered by GPL

Coding:

• increase gcc warning level
• add required #includes
• remove spurious commas in bison token lists
• drop worthless malloc() casts; see C-faq/q7.7
• prototype yylex and yyerror
• add braces around confusing if/else chain

April 20, 2008
Larry Doolittle